The present invention relates to a technique which is effective when applied to semiconductor integrated circuits, for example, a logic semiconductor integrated circuit whose input and output levels are TTL levels and whose internal logic levels are CMOS levels.
FIG. 1 shows a block diagram of a logic semiconductor integrated circuit IC having TTL levels as its input and output levels and CMOS levels as its internal logic levels, which circuit was studied by the inventors before the present invention.
Such circuit IC includes an input buffer 10 for level-converting input signals of TTL levels IN.sub.1, IN.sub.2, . . . IN.sub.n into signals of CMOS levels, an internal logic block 11 for executing logic operations with the CMOS levels, and an output buffer 12 for level-converting the CMOS level output signals of the internal logic block 11 into output signals of TTL levels OUT.sub.1, OUT.sub.2, . . . OUT.sub.m. The respective circuits 10, 11 and 12 are fed with a supply voltage V.sub.CC of 5 volts, and are properly grounded.
A high level input voltage V.sub.iH10 to be supplied to the input terminals IN.sub.1, IN.sub.2, . . . IN.sub.n of the input buffer 10 is set at 2.0 volts or above, while a low level input voltage V.sub.iL10 is set at 0.8 volt or below. Accordingly, an input threshold voltage V.sub.ith10 concerning the input terminals IN.sub.1, IN.sub.2, . . . IN.sub.n of the input buffer 10 is set at 1.3-1.5 volt which is between 0.8 volt and 2.0 volts.
On the other hand, a high level output voltage V.sub.oH10 to be derived from the output of the input buffer 10 is set to be equal to the high level input voltage V.sub.iH11 of the internal logic block 11, while a low level output voltage V.sub.oL10 to be derived from the output of the input buffer 10 is set to be equal to the low level input voltage V.sub.iL11 of the internal logic block 11. Accordingly, letting V.sub.TP and V.sub.TN denote the threshold voltages of a P-channel MOS FET and an N-channel MOS FET which constitute a CMOS inverter in the internal logic block 11, respectively, and V.sub.CC denote the supply voltage, the above voltages V.sub.oH10, V.sub.iH11, V.sub.oL10 and V.sub.iL11 are respectively set as follows: EQU V.sub.oH10 =V.sub.iH11 &gt;V.sub.CC -.vertline.V.sub.TP .vertline.(1) EQU V.sub.oL10 =V.sub.iL11 &lt;V.sub.TN ( 2)
When V.sub.CC is set at 5 volts, .vertline.V.sub.TP .vertline. at 0.6 volt and V.sub.TN at 0.6 volt, V.sub.oH10 and V.sub.iH11 are set at above 4.4 volts, and V.sub.oL10 and V.sub.iL11 at below 0.6 volt.
Accordingly, the input logic threshold voltage V.sub.ith11 of the CMOS inverter in the internal logic block 11 is set at approximately 2.5 volts which is between 0.6 volt and 4.4 volts.
Likewise, the high level output voltage V.sub.oH11 of the internal logic block 11 and the high level input voltage V.sub.iH12 of the output buffer 12 are set at above 4.4 volts, the low level output voltage V.sub.oL11 of the internal logic block 11 and the low level input voltage V.sub.iL12 of the output buffer 12 are set at below 0.6 volt, and the input logic threshold voltage V.sub.ith12 of the output buffer 12 is set at approximately 2.5 volts which is between 0.6 volt and 4.4 volts.
In order to generate the output signals of TTL levels, the output buffer 12 has its high level output voltage V.sub.oH12 set at 2.7 volts or above and its low level output voltage V.sub.oL12 at 0.5 volt or below.
FIG. 2 is a circuit diagram showing one input buffer 10 which was constructed and studied by the inventors for test purposes before the present invention, and which is constructed of P-channel MOS FETs M.sub.p1, M.sub.p2, N-channel MOS FETs M.sub.n1, M.sub.n2, M.sub.n3, and a resistor R.sub.p. The gates sources and drains of the MOS FETs are respectively indicated by symbols g, s and d.
A first stage CMOS inverter composed of the FETs M.sub.p1 and M.sub.n1, an da second stage CMOS inverter composed of the FETs M.sub.p2 and M.sub.n2 are connected in cascade. The components R.sub.p and M.sub.n3 constitute a gate protection circuit for protecting the gate insulating films of the FETs M.sub.p1 and M.sub.n1. An output capacitance C.sub.s connected to the drains of the FETs M.sub.p2 and M.sub.n2 of the second stage CMOS inverter has, in actuality, its value determined by the drain capacitances of the FETs M.sub.p2 and M.sub.n2, the wiring stray capacitance between the output of the input buffer 10 and the input of the internal logic block 11, and the input capacitance of the internal logic block 11.
The ratios W/L between the channel widths W and channel lengths L of the MOS FETs M.sub.p1, M.sub.p2, M.sub.n1, M.sub.n2 and M.sub.n3 are respectively set at 27/3.5, 42/3, 126/3.5, 42/3 and 15/3. The resistor R.sub.p is set at a resistance of 2 kiloohms.
FIG. 3 illustrates the dependencies of the propagation delay times t.sub.pHL, t.sub.pLH of the input buffer 10 of FIG. 2 upon the output capacitance C.sub.s. In the figure, the axis of ordinates represents the propagation delay times, while the axis of abscissas represents the output capacitance C.sub.s. FIG. 3 also shows delay time dependencies for the buffers of FIGS. 14, 19, 22 and 31, as will be discussed in detail later.
A definition of the propagation delay times used in FIG. 3 and throughout this specification is shown in FIG. 35. As illustrated in FIG. 35, the first propagation delay time t.sub.pHL is defined as a period of time which elapses from the time that an input INPUT to the buffer reaches its 50% value until the time an output OUTPUT from the buffer changing from a high level to a low level reaches its 50% value. The second propagation delay time t.sub.pHL is defined as a period of time which elapses from the time the input INPUT to the buffer reaches its 50% value until the time when output OUTPUT from the buffer changing from the low level to the high level reaches its 50% value. In FIG. 35, t.sub.f is defined as a fall time, and t.sub.r as a rise time between the 10% and 90% values of the output of the buffer.
Thus, as understood from FIG. 3, the output capacitance-dependency K.sub.HL (=.DELTA.t.sub.pHL /.DELTA.C.sub.s) of the first propagation delay time t.sub.pHL of the input buffer 10 in FIG. 2 is about 0.8 nsec/pH, and the output capacitance-dependency K.sub.LH (=.DELTA.t.sub.pHL /.DELTA.C.sub.s) of the second propagation delay time t.sub.pLH is about 1.4 nsec/pF. Both of these values are relatively large.
In the input buffer 10 of FIG. 2, in order to set the input threshold voltage V.sub.ith10 at approximately 1.3-1.5 volt, the ratios W/L between the channel widths and channel lengths of the FETs M.sub.p1 and M.sub.n1 of the first stage CMOS inverter are made greatly different, and in order to lessen the output capacitance-dependencies K.sub.HL and K.sub.LH of the respective propagation delay times t.sub.pHL and t.sub.pLH, both the ratios W/L of the FETs M.sub.p2 and M.sub.n2 of the second stage CMOS inverter are set at the large value of 42/3 so as to increase the channel conductances of these FETs M.sub.p2 and M.sub.n2.
To the end of reducing both the output capacitance-dependencies K.sub.HL and K.sub.LH, the ratios W/L of the FETs M.sub.p2 and M.sub.n2 of the second stage CMOS inverter may be increased more and more. This, however, incurs a conspicuous increase in the occupation area of the input buffer 10 on the surface of an integrated circuit chip for the following reason, to form an obstacle to enhancement in the density of integration.
In the production technology of integrated circuits, fining is being vigorously promoted at present. With the present-day photolithography based on exposure to ultraviolet radiation, however, the channel length L of a MOS FET is often set with 3 .mu.m as its practical lower limit value. In order to set the ratio W/L of the MOS FET at a very large value, therefore, the channel width W thereof must be set at an extraordinary large value. Eventually, the device area of the MOS FET increases conspicuously.
FIG. 4 is a circuit diagram showing one output buffer 12 which was constructed and studied by the inventors for test purposes before the present invention and which is constructed of a P-channel MOS FET M.sub.p4 and an N-channel MOS FET M.sub.n4. The gates, sources and drains of the MOS FETs are respectively indicated by symbols g, s and d.
In the integrated circuit IC, the output signal of CMOS level from the internal logic block 11 is applied to the gates of the FETs M.sub.p4 and M.sub.n4 of the output buffer 12. Terminal No. 30 is fed with the supply voltage V.sub.CC of 5 volts. In order to set the input logic threshold voltage V.sub.ith12 of the output buffer 12 at approximately 2.5 volts, accordingly, the ratios W/L of the FETs M.sub.p4 and M.sub.n4 are set at values equal to each other.
FIG. 4 also shows a TTL circuit 14, which is fed with the supply voltage V.sub.CC of 5 volts through terminal No. 35. The output signal of TTL level from the output buffer 12 is derived from terminal No. 20, and is supplied to one emitter of the multi-emitter transistor Q.sub.1 of the TTL circuit 14 through terminal No. 32.
A variety of TTL circuits are presently known from publications in the art including a standard TTL circuit, a Schottky TTL circuit, a low power Schottky TTL circuit and an advanced low power Schottky TTL circuit. Naturally, the characteristics of these circuits are somewhat different from one another.
The output of the output buffer 12 needs to drive a large number of inputs of the TTL circuit 14 at the same time and in parallel. A criterion for the drive ability is to be capable of driving 20 inputs of a low power Schottky TTL circuit in parallel.
When the output of the output buffer 12 is at its low level, a low level input current I.sub.IL of 0.4 mA flows from one input of the low power Schottky TTL circuit into the drain-source path of the N-channel MOS FET M.sub.n4 of the output buffer 12. Accordingly, the FET M.sub.n4 needs to pour a total of 8 mA in order that the output buffer 12 may drive the aforementioned 20 inputs to the low level.
On the other hand, the low level output voltage V.sub.oL12 of the output buffer 12 must be 0.5 volt or below as already explained. Therefore, the ON-resistance R.sub.ON of the N-channel MOS FET M.sub.n4 of the output buffer 12 must be set at a small value of 0.5 volts8 milliampere=62.5 ohms or so.
In order to make the ON-resistance R.sub.ON of the FET M.sub.n4 such a low resistance, the ratio W/L of the FET M.sub.n4 must be set at a very large value of 700/3 to 1000/3. Meanwhile, as stated above, both the ratios W/L of the FETs M.sub.p4 and M.sub.n4 need to be equal values for the purpose of setting the input logic threshold voltage V.sub.ith12 of the output buffer 12 at approximately 2.5 volts. Therefore, also the ratio W/L of the P-channel MOS FET M.sub.p4 of the output buffer 12 must be set at the very large value of 700/3 to 1000/3.
This fact similarly brings about a conspicuous increase in the occupation area of the output buffer 12 on the surface of the integrated circuit chip, to hamper enhancement in the density of integration. Moreover, it incurs drastic lowering in the switching speed of the internal logic block 11 for the following reason.
When both the ratios W/L of the two MOS FETs M.sub.p4 and M.sub.n4 of the output buffer 12 are set at the large values noted above, the gate capacitances of these MOS FETs become large values proportionally. Since the gate capacitances of the FETs M.sub.p4 and M.sub.n4 constitute the output load capacitance of the internal logic block 11, these gate capacitances and the output resistance of the internal logic block 11 incur the lowering of the switching speed of the internal logic block 11.
Meanwhile, since the output of the output buffer 12 is not only derived from the external output terminal (terminal No. 20) of the integrated circuit IC, but also connected to the large number of input terminals of the TTL circuit 14 through external wiring, the output load capacitance C.sub.x of the output buffer 12 often becomes a very large value.
FIG. 5 illustrates the dependencies of the propagation delay times t.sub.pHL, t.sub.pLH upon the output load capacitance C.sub.x of the output buffer 12 in FIG. 4. In the graph of FIG. 5, the axis of ordinates represents the propagation delay times, while the axis of abscissas represents the output load capacitance. FIG. 5 also shows such delay time dependencies for FIG. 34, as will be discussed later.
Thus, as understood from FIG. 5, the capacitance-dependency K.sub.HL (=.DELTA.t.sub.pHL /.DELTA.C.sub.x) of the first propagation delay time t.sub.pHL of the output buffer 12 in FIG. 4 is about 0.3 nsec/pF, and the capacitance-dependency K.sub.LH (=.DELTA.t.sub.pLH /.DELTA.C.sub.x) of the second propagation delay time t.sub.pLH is about 0.17 nsec/pF. Both of these are undesirably large.
Accordingly, the input buffer 10 of FIG. 2 which the inventors tested in development of the present invention involves problems as summed up below.
(1) In order to lessen the output capacitance-dependencies of the propagation delay times of the input buffer 10, the ratios W/L of both the MOS FETs M.sub.p2 and M.sub.n2 of the second stage CMOS inverter of the input buffer 10 must be made large, which hampers enhancement in the density of integration. Particularly in a case where the integrated circuit IC is of the master slice type or the semi-custom gate array type, there is the possibility that a very large number of gate input terminals in the internal logic block 11 will be connected to the output of the input buffer 10. When the output capacitance C.sub.s of the input buffer 10 accordingly becomes very great, the above problem is very serious. PA0 (2) Further, the first stage of the input buffer 10 is formed of the CMOS inverter M.sub.p1, M.sub.n1. Therefore, even when the gate protection circuit composed of the elements R.sub.p and M.sub.n3 is connected, the breakdown strengths of the gate insulating films of both the MOS FETs M.sub.p1, M.sub.n1 against a surge voltage applied to the input terminal IN.sub.1 are not satisfactory. PA0 (3) In order to set the input logic threshold voltage V.sub.ith12 of the output buffer 12 at approximately 2.5 volts and to enhance the current sink ability at the low level output of the output buffer 12, the ratios W/L of both the MOS FETs M.sub.p4 and M.sub.n4 must be set at large values equal to each other, which hampers enhancement in the density of integration. PA0 (4) When the ratios W/L of both the MOS FETs M.sub.p4 and M.sub.n4 of the output buffer 12 are made large, the gate capacitances of these MOS FETs also increase. In consequence, these gate capacitances and the output resistance of the internal logic block 11 incur lowering in the switching speed of the internal logic block 11. Particularly in a case where the output stage of the internal logic block 11 is composed of MOS FETs of high output resistance, the lowering of the switching speed is conspicuously problematic. PA0 (5) Since the output buffer 12 is composed of the MOS FETs M.sub.p4 and M.sub.n4, the dependencies of the propagation delay times upon the output load capacitance C.sub.x are great. Particularly in a case where a large number of input terminals of the TTL circuit 14 are connected to the output of the output buffer 12, this problem becomes important.
In addition, the output buffer 12 of FIG. 4 which the inventors tested in the development of the present invention involves problems as summed up below.